This invention relates to Electronic Design Automation (EDA) systems, and particularly to a method for graphically identifying registers with unbalanced slack during placement driven synthesis optimization.
EDA tools are used to aid in the development of integrated circuits. The placement driven synthesis tool is used to optimize a given set of logic gates to meet physical, timing, electrical, area, and power constraints. During the development process it is common to see a timing violation (i.e., negative slack) on the input of a latch and not the output, or vice versa. Such a scenario may be the result of poor placement, poor optimization, or poor logic design.
Currently, latches with “unbalanced” slacks can be optimized using EinsTimer's clock skew scheduling. Einstimer attempts to balance the slacks as best it can by adjusting the arrival time of the clock. A textual report is generated and the in-core design can be updated with these new constraints. However, a textual report is missing vital information such as the placement of the latches. Even if the report were to include placement locations, it would be quite difficult to visualize. The EinsTimer report does generate an image, but it is only a two-dimensional graph showing a histogram of the modified skews, it does not plot the design itself. Additional optimizations attempt to balance slack by replacing the latch or its associated logic cone. These optimizations modify the netlist without visualizing how the optimization performed. In some cases, a textual report is issued which is still inadequate.
These latches could be identified using an interactive physical design browser, such as, IBM Chipbench. While this browser aids in debug, there can be substantial runtime to load the design into a proper timing environment. Also, the interactive browser only depicts the current state of the netlist and cannot easily compare before and after effects of an optimization from placement driven synthesis.